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Senior Semiconductor Design Engineer
Aarambh Silicon
- Full-time
- Hybrid
- Electronics
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Posted 16 Jul 2026
About the role
Own the physical design flow for a mixed-signal SoC heading to tape-out in Q2 next year.
What you will do
- Drive floorplanning, placement, CTS and routing to timing closure
- Own signoff for timing, power and physical verification
- Mentor two junior engineers through their first tape-out
- Work with the analog team on integration boundaries
What we are looking for
- B.Tech or M.Tech in electronics, electrical engineering or equivalent
- At least two tape-outs at 16nm or below
- Fluency with Innovus or ICC2, PrimeTime and Calibre
- Scripting in TCL and Python